Front-surface N+ gettering techniques for reducing noise in integrated circuits

ABSTRACT

Large &#34;inactive&#34; N+ regions are provided in P channel junction field effect transistors (JFETs) or NPN transistors immediately adjacent to &#34;active&#34; areas thereof to getter impurities away from the active areas. The ratio of inactive N+ area to the total area of the transistors is selected to provide suitably low noise measurements at low frequencies. Low noise amplifier circuitry is provided wherein all transistors in the AC signal path include unusually large ratios of inactive N+ area to total transistor area in order to provide greatly reduced low frequency noise levels.

BACKGROUND OF THE INVENTION

The invention relates to techniques and structures for front-surfacegettering of impurities in integrated circuits.

It should be noted that the precise mechanisms involved in gettering arenot well understood, and numerous technical articles have been writtendirected to this subject setting forth various, sometimes inconsistent,theories.

So-called "gettering" techniques introduce low energy sites into asemiconductor crystal lattice structure so that at high temperatures,various fast diffusing impurities, especially heavy metallic impuritiessuch as copper, iron, and gold will be trapped. It is highly desirablein semiconductor devices to trap such heavy metallic impurities inlocations remote from the "active" regions of semiconductor devicesbecause otherwise such metallic impurities represent minority carriersites that result in frequent generation and recombination of minoritycarriers in the active regions. Such generation and recombination ofminority carriers in active regions of a transistor produces noise incurrents flowing through the transistor. Such noise includes the typesometimes referred to as "popcorn" noise or "burst" noise, and alsoincludes 1/f noise, both of which ae highly undesirable in semiconductordevices such as JFETs and NPN transistors, etc. that are used in highgain, low noise amplifier circuits. Various techniques have beenproposed or utilized for gettering unwanted impurities fromsemiconductors. Such techniques have included introducing highlystressed or damaged regions in the semiconductor single crystal latticestructure by diffusing or implanting ions into front and/or backsurfaces of integrated circuit wafers. Such damage produces low energysites in the semiconductor lattice structure that act as traps for fastdiffusing metallic impurities when the semiconductor wafer temperatureis elevated to appropriate gettering temperatures.

Perhaps the closest prior art is indicated by U.S. Pat. No. 3,874,936and by "Gettering Technique and Structure", by Bogardus, et al., IBMTechnical Disclosure Bulletin Vol. 16, No. 4, September, 1983, page1066. U.S. Pat. No. 3,874,936 discloses creating top surface stressedareas on a semiconductor wafer by providing boron diffusions within bothN+ emitter regions and N+ collector contact regions in NPN transistors.The Bogardus disclosure shows the technique of creating highly damagedring-shaped regions in the base and collector regions of NPN transistorsto provide top surface gettering of impurities in an integrated circuitstructure. The disclosed techniques require steps additional to those ofstandard integrated circuit processes, adding considerably to the costof manufacture of the integrated circuits. The above references teachthat the gettering achieved reduces the occurrence of "soft" PNjunctions and increases yields. The references do not teach that use offront-surface gettering of any kind is practical as a means of reducingthe noise of bipolar transistors, field effect transistors, orintegrated circuits containing such devices.

It is thought that the prior art includes bipolar transistor devices inwhich N+ rings have been utilized in the collector region for thepurpose of reducing series collector resistance. It also is believedthat the prior art includes NPN transistor structures in which N+ ringshave been formed within the base region and electrically shorted theretofor the purpose of reducing minority carrier storage time to increasetransistor switching speeds.

There is an unmet need for an improved technique of substantiallyreducing the noise produced in integrated circuits manufactured byconventional integrated circuit manufacturing processes withoutsubstantially increasing the number of processing steps or the cost ofthe overall manufacturing process. For example, the assignee hasexperienced yield losses of two to five percent of certain low noiseoperational amplifier circuits and the like due to failure to pass lowfrequency noise tests.

SUMMARY OF THE INVENTION

It is an object of the invention to provide a technique for reducing theamount of low frequency noise in a semiconductor device.

It is another object of the invention to provide a gettering techniquefor reducing low frequency noise in bipolar transistors and field effecttransistors without significantly increasing the cost of integratedcircuits containing them.

Briefly described, and in accordance with one embodiment thereof, theinvention provides a low noise semiconductor device, such as a junctionfield effect transistor (JFET) of bipolar transistor, including featuresfor reducing noise in the semiconductor device by providing a pluralityof regions in a top surface of the semiconductor device within a firstregion, some of the regions defining an active region in which currentflows to cause the semiconductor to operate and in whichrecombination-generation centers including heavy metallic impuritiesexist, the semiconductor device including a gettering region ofinactive, heavily doped material in an area of the top surface that liesoutside of an adjacent to the active region, wherein the getteringregion occupies at least about 25 percent of the top surface area of thefirst region. In some of the the described embodiments of the invention,the inactive, heavily doped gettering region occupies as much as about75 percent of the top surface area of the first region. In the describedembodiments of the invention, the gettering region is filled with N+impurities which are introduced into the top surface during the sameprocess in which N+ emitter region impurities are introduced into otherareas of the surface. In one described embodiment of the invention,relatively large N+ gettering regions are formed adjacent to and/orsurrounding the channel region of a P channel junction field effecttransistor in an integrated circuit structure. In another embodiment ofthe invention, an N+ gettering regions surrounds the emitter-basejunction of a NPN transistor in an integrated circuit structure and isdisposed within the base region thereof, and another larger N+ getteringregion is disposed in the N type epitaxial N type island in which thebase region is formed. Suitable temperature ramping cycles are providedto allow fast diffusing metallic impurities in the vicinity of theactive region of the semiconductor device to diffuse to the N+ getteringregions, reducing the concentration of such metallic impurities in theactive region of the semiconductor device, thereby reducing noise due torecombination-generation of minority carriers in the active regions ofsemiconductor devices such as NPN transistors and P channel JFETs.

A high gain, low noise amplifier is described in which all transistorsin the AC signal path from the input through the high gain portion ofthe amplifier contain N+ gettering regions adjacent to their activeregions, wherein each of the N+ gettering regions occupies from about 25percent to about 75 percent of the surface area of the N type region inwhich the transistor is formed. A substantial decrease in the totalnoise voltage in the circuit is achieved, due to an even greaterreduction in the low frequency noise component therein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a section view of a conventional NPN transistor.

FIG. 1B is a plan view of the prior art transistor shown in FIG. 1.

FIG. 1C is a section view of a conventional JFET (junction field effecttransistor).

FIG. 1D is a partial plan view of the JFET of FIG. 1C.

FIG. 2A is a plan view of a standard JFET utilized in experimentsleading to the present invention.

FIG. 2B is a plan view of an N+ enhanced JFET similar to that of FIG. 2Aand having a large inactive N+ gettering region in accordance with thepresent invention.

FIG. 3A is a plan view of a conventional NPN integrated circuittransistor used in experiments leading in the present invention.

FIG. 3B is a plan view of an NPN integrated circuit transistorcontaining a large N+ gettering region in accordance with the presentinvention.

FIG. 4A is a plan view of another junction field effect transistorstructure having a large ratio of inactive N+ region to total transistorarea in accordance with the present invention.

FIG. 4B is a plan view of another junction field effect transistorhaving a relatively large inactive N+ gettering region.

FIG. 5 is a schematic diagram of a low noise amplifier including the N+enhanced junction field effect transistors shown in FIGS. 4A and 4B inthe high gain portion of the AC signal path.

FIGS. 6A and 6B are plan views of junction field effect transistors withdifferent ratios of inactive N+ gettering area to total transistor area,used in experiments leading to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Before describing the several embodiments of the invention, it firstwill be helpful to describe a conventional integrated circuit NPNtransistor and a conventional integrated circuit P channel JFET.Referring to FIGS. 1A and 1B, a typical bipolar integrated circuitstructure is shown. A lightly doped N type region 11 disposed on a Ptype substrate is isolated from other such lightly doped N type regions(not shown) by a deep P+ isolation diffusion 15. A P type base region 12is diffused into the N region 11. Subsequently, N+ emitter region 13 andN+ collector contact regions 14 are diffused into base region 12 and N⁻"collector" region 11, respectively. In some processes, an N+ getteringlayer 10 is formed on the bottom of the P type substrate to getterimpurities, to reduce low frequency noise. This, of course, cannot bedone for dielectrically isolated integrated circuits.

In FIGS. 1C and 1D, a conventional prior art P channel JFET of the typecommonly included with NPN bipolar transistors in an integrated circuitmanufacturing process is illustrated. The P channel JFET is formedwithin an N⁻ epitaxial region 17A. The source region 26 and drain region28 are formed at the same time that the base regions of NPN transistorselsewhere in the circuit are formed. An N+ gate contact region 25 isformed outside of the channel region between source and drain regions 26and 28 at the same time that the emitter regions are formed elsewhere inthe circuit. Then a gate mask opening 23A is formed in the thick fieldoxide on the upper surface of the circuit, and a thin oxide layer 9 isformed to improve the quality of a subsequent N type gate implantingoperation.

Next, a photoresist mask is applied to the upper surface to leave only achannel region 24A exposed, and a boron channel implanting operation isperformed to produce a lightly doped P⁻ channel region 18 between thesource and the drain. (Typically, the concentration of the channel mightbe 5×10¹⁶ to 7×10¹⁶ atoms per cubic centimeter.) The channel mask ofphotoresist then is removed, and an arsenic implant step is performed toproduce an N type gate region 18 within gate opening 23A. (Theconcentration of the arsenic doped gate layer might be from about 1×10¹⁷to 5×10¹⁷ atoms per cubic centimeter. This is not high enough tocompensate the surface of the P type source and drain regions 26 and28.) The arsenic doped layer 17B forms the top gate electrode of theJFET, the bottom gate electrode being formed by the N⁻ epitaxial region17A. (The P⁻ channel region 18 is pinched off in the proportion to thevoltage applied to gate contact region 25 relative to the voltageapplied to the source region 16A.)

By way of definition, in the NPN transistor of FIGS. 1A and 1B, the"active" region is considered to include the emitter-base junction andregions immediately adjacent thereto, wherein minority carriers areinjected by the emitter into the base to form the collector current. Thepresence of recombination-generation centers in this active region leadsto the above-described low frequency "popcorn" noise and 1/f noise inthe collector current, which is highly undesirable for low noisecircuits. In the JFET of FIGS. 1C and 1D, the "active" region in the P⁻channel region 18. Presence of recombination-generation centers in thechannel region causes low frequency 1/f noise in the drain current,which also is undesirable for low noise circuits.

Although the N+ collector contact region 14 and the emitter region 13 ofthe conventional bipolar transistor of FIGS. 1A and 1B inherently getterfast diffusing metallic impurities during certain portions ofconventional integrated circuit manufacturing processes, theconcentration of such metallic impurities in the active regions clearlyis not adequate to prevent substantial yield losses in low noiseintegrated circuits. Similarly, the N+ gate contact region 25 in theJFETs of FIGS. 1C and 1D getters some of the heavy metallic impuritiesin the channel region, but not nearly enough to reduce the noise levelin low noise circuits sufficiently to avoid substantial yield losses. Itis believed that the N+ emitter regions, collector contact regions, andN+ gate contact regions tend to attract fast diffusing metallicimpurities into the active regions of such transistors. The N+ regionssuch as 10 in FIG. 1A on the bottom surface of wafers have beeninadequate to reduce the concentration of heavy metallic impurities inthe active regions of the transistors enough to reduce low frequencynoise to acceptably low levels.

Now that the basic JFET and NPN transistor structures of conventionalintegrated circuit manufacturing processes are well understood, theexperiments leading to the present invention can be easily understood.In accordance with the present invention, experiments were performed todetermine if substantial improvements in yield of certain low noiseintegrated circuits could be achieved by "front surface gettering".Substantial amounts of additional heavily damaged, electrically"inactive" emitter-type N+ areas were provided in the N⁻ epitaxialregions of JFETs and bipolar transistors but outside of the activeregions thereof to determine if enough metallic impurities could begettered away from the active regions to substantially reduce lowfrequency noise therein.

To perform the experiments, a pair of JFET devices 21 and 21A shown inFIGS. 2A and 2B, respectively, were constructed. The JFET 21 in FIG. 2Ais referred to hereafter as a "standard" JFET and JFET 21A is referredto herein as an "N+ enhanced JFET". Both standard JFET 21 and N+enhanced JFET 21A are formed in a respective dielectrically isolated N⁻epitaxial region designated by reference numeral 32. (However, for N+enhanced JFET 21A, the top surface area of the N type epitaxial region32 is substantially larger than that of standard JFET 21.) Both standardJFET 21 and N+ enhanced JFET 21A have a plurality of separate P typesource regions 28, all of which are electrically connected together by ametal conductor 30A that is also connected to a source electrode 30B.(The reason that separate source regions are utilized rather than asingle long source region, is to make "scaling" of the geometry of theJFET more convenient.)

Both standard JFET 21 and N+ enhanced JFET 21A include a plurality ofseparate P type drain regions 28, all of which are electricallyconnected together by a metal conductor 29A that also is connected to adrain electrode 29B. (The contact openings of conductors 29A to the Ptype drain regions 28 and the contact openings allowing connection ofthe source regions 26 to metal conductor 30A are indicated by dottedlines.) In both JFETs 21 and 21A, the N type gate region is designatedby reference numeral 23, and P type channel regions are designated byreference numeral 24A. The N+ gate contact regions 25A, 25B, and 25C allare connected by metal conductor 27A to a gate electrode 27B.

The only difference between standard JFET 21 and N+ enhanced JFET 21A isthe increased size of the epitaxial N type region 32 and the provisionof a large N+ gettering ring 33 in N+ enhanced JFET 21A. Gettering ring33 is formed of the same N+ material as gate contact regions 25A, 25B,and 25C, and extends as closely as permissable (i.e., about 0.2 mils)according to good design practice to the edge of the epitaxial N⁻¹region 32.

In accordance with the present invention, the area of N+ getteringregion 33 is about 25 to 75 percent of the total area of the epitaxialN⁻ region 32, and preferably is about 50 percent thereof. Morespecifically, in the standard JFET of FIG. 2A, the total area ofepitaxial N⁻ type region 32 is 63.84 square mils, and the total inactiveN+ area is 14.4. square mils, producing a 23 percent ratio of inactiveN+ area to total epitaxial N⁻ area. For the N+ enhanced JFET shown inFIG. 2B, the total epitaxial N⁻ area is 165.06 square mils, and thetotal inactive N+ area is 115.52 square mils, so the ratio of inactiveN+ area to total epitaxial area is 70 percent.

Using identical processing procedures, a number of samples of each ofJFETs 21 and 21A were fabricated and then tested for low noiseperformance with drain currents of 200 microamperes. (Drain currents of200 microamperes were selected so that the recombination-generationcomponents of the noise would not be dwarfed by the so-called g_(m)noise.)

The noise voltage measurements of each JFET were made at frequencies of10 hertz, 100 hertz, 1 kilohertz, 10 kilohertz, and 100 kilohertz,utilizing a Quan-Tec transistor noise analyzer Model 2173C, manufacturedby Quan-Tec, a division of KMS Industries, Flander, N.J.

Although very little difference was found in the noise voltagemeasurements of JFETs 21 and 21A at frequencies above 1 kilohertz, atlower frequencies the noise voltage measurements of N+ enhanced JFETs,such as 21A were significantly lower. For a sample of 30 devices, halfof which were identical to standard JFET 21 and the other half of whichwere identical to N+ enhanced JFET 21A, the mean measured noise voltageat 10 hertz was 12.33 nanovolts for standard JFET 21, with a standarddeviation of 1.68 nanovolts. The mean noise voltage measured at 10 hertzfor N+ enhanced JFET 21A was much lower, at 9.53 nanovolts, with astandard deviation of 1.58 nanovolts. This indicates a 23 percentreduction in total measured noise at 10 hertz achieved by providing thelarge amount of inactive N+ area 33 immediately adjacent to the activeregion (i.e., the channel region 18) of N+ enhanced JFET 21A.

At 100 hertz, the mean measured noise voltage for the standard JFETs 21was 10.30 nanovolts, with a standard deviation of 0.775. The meanmeasured voltage for the N+ enhanced JFETs 21A again was much lower, at8.60 nanovolts, with a standard deviation of 8.28.

For noise voltage measurements at 1 kilohertz, the mean measured noisefor the standard JFETs 21 was 5.39 nanovolts with a standard deviationof 0.21 nanovolts. The mean measured noise for the N+ enhanced JFETs 21Awas only slightly lower, at 5.22 nanovolts, with a standard deviation of0.20 nanovolts.

Although a slight difference in the mean measured noise voltages wasfound to exist at 1 kilohertz, the difference is not nearly as great asthe difference between the standard and N+ enhanced JFETs at the lowerfrequencies. This result is consistent with the fact that noise due tominority carrier generation-recombination mechanisms (which is what iscaused by metallic impurities such as iron, copper, etc. in thesemiconductor material) is present mainly at the lower frequencies. Ifsufficiently increased amounts of the metallic impurities actually aregettered to the inactive N+ gettering region 33 of N+ enhanced JFET 21A,this would cause its low frequency noise voltage to be substantiallyless than that of standard JFET 21, which is what is observed above.

FIG. 5 shows a low noise operational amplifier circuit including JFETs48A, 48B, 56A, 56B, and 56C in the AC signal path in the high gainsections of the circuit in which low frequency noise would be mostdamaging to overall noise performance of the amplifier. JFETs 48A and48B were implemented using a JFET structure essentially similar to theenhanced N+ JFET structure 21B shown in FIG. 4A. The various parts of N+enhanced JFET 21B are designated by the same reference numerals as inFIG. 2B. JFETs 56A, 56B, and 56C are implemented by means of N+ enhancedJFET 21C in FIG. 4B, wherein the various elements are designated by thesame reference numerals as in FIG. 2B. (Due to the location of availablearea in a preexisting mask set for the operational amplifier of FIG. 5,the large N+ gettering regions 33 in input transistors 21B of FIG. 4Aand JFET 21C of FIG. 4B are not in the form of rings symmetricallysurrounding the active channel regions. Instead, the N+ getteringregions 33 are along side of the active channel area as shown.) Notethat the precise configuration of the various components in FIG. 5 isnot relevant to the invention. Those skilled in the art can easilyrecognize the high gain signal path and the functions of the variousbias circuits, differential stages, and output stage of the operationalamplifier, so they are not described in detail.

After the preexisting mask set was altered to provide the above JFETstructures, a wafer run was fabricated in which half of the wafers inthe lot utilized the original JFET structure without the N+ getteringregions 33. The other half of the wafers were manufactured using masksets that do produce the N+ gettering regions 33 as described above.

After processing, all of the wafers were tested for noise voltagereadings at 10 hertz. The 10 hertz noise voltage measured at the outputconductor 80 of the amplifier circuit shown in FIG. 5 for the circuitshaving standard JFETs was 59.46 nanovolts. The average noise voltagemeaured in those circuits of the same processing run manufactured withN+ enhanced JFETs of FIGS. 4A and 4B was only 36.7 nanovolts.

The results of the foregoing experiments for the circuit of FIG. 5indicate that in low noise circuits, use of transistors (either JFETs orbipolar transistors) with N+ gettering regions that occupy from about 25percent to about 75 percent of the epitaxial N type region (in which theJFET or bipolar transistor is fabricated) to implement all transistorsin the AC signal path through the input stage and any successive highgain stages should substantially reduce low frequency noise.

The JFET 21B of FIG. 4A has 78 percent of the surface area of theepitaxial N type region 32 filled with N+ gettering region 33. JFET 21Dof FIG. 6A has 22 percent of the surface of its N type epitaxial region32 filled with N+ gettering region 33. JFET 21E of FIG. 6B has only 6.6percent of its N type epitaxial region 33 filled with N+ region 33.

Using JFETs 21B, 21D, and 21E all of which were fabricated in the samewafer run, another experiment was performed in which noise measurementsat drain currents of 200 microamperes were measured at 10 hertz, 100hertz and 1 kilohertz. The mean noise voltages measured for the JFETs21B of FIG. 4A, 21D of FIG. 6A, and 21E of FIG. 6B are indicated in thefollowing table:

                                      TABLE 1                                     __________________________________________________________________________            JFET 21B    JFET 21D    JFET 21E                                      FREQUENCY                                                                             (78% INACTIVE N+)                                                                         (22% INACTIVE N+)                                                                         (6.6% INACTIVE N+)                            __________________________________________________________________________     10 hertz                                                                             21.33 nanovolts                                                                           26.0  nanovolts                                                                           39.83 nanovolts                               100 hertz                                                                             37.5  nanovolts                                                                           42.67 nanovolts                                                                           47.67 nanovolts                                1 kHz  12.0  nanovolts                                                                           12.0  nanovolts                                                                           14.08 nanovolts                               __________________________________________________________________________

The above figures show that at low frequencies, the noise voltage is astrong function of the ratio of the inactive N+ gettering region area tothe total surface area of the N type epitaxial region of the transistor,and that at least about 20 to 25 percent of the N type epitaxial region(in which the transistor is formed) should be filled with inactiveemitter diffusion type N+ material that has a heavily damaged surfacestructure.

Although most of the experiments performed were with P channel JFETs asdescribed above, a similar analysis has been performed for bipolar NPNtransistors. FIG. 3A shows a standard NPN transistor 7, having basicallythe structure shown in FIGS. 1A and 1B. FIG. 3B shows another NPNtransistor that is referred to herein as N+ enhanced NPN transistor 7A.Its base, emitter, and base contact regions are essentially identical,except that the structure in FIG. 3B has a substantially largerepitaxial N type region 32 and an N+ gettering ring 33 formed around itsimilar to the gettering rings described above for the JFET devices, andalso has an N+ gettering ring 12A formed in the P type base regin 12 andelectrically shorted to the base region 12 by metal 5A through theenlarged base contact openings 12B.

The percentage of the surface area of the epitaxial N type region 32 forstandard NPN transistor 7 that is occupied by inactive N+ materialconstituting the N+ collector contact region 14 is about 7 percent. Inthe N+ enhanced NPN transistor 7A of FIG. 3B, the percentage of thesurface of epitaxial of N type region 32 occupied by N+ gettering region33 should be at least about 20 to 40 percent.

It should be noted that the device shown in FIG. 3B has not actuallybeen constructed and tested yet. Instead, a similar device having anarrower N+ ring structure for N+ region 33, in which inactive N+material occupies only about 35 percent of the epitaxial N type region33, was constructed and tested. That device and the device shown in FIG.3A were fabricated in the same wafer run and subjected to noise voltagetests at 10 hertz, 100 hertz, and 1 kilohertz, and produced thefollowing results:

                                      TABLE 2                                     __________________________________________________________________________            STANDARD NPN TRANSISTOR                                               FREQUENCY                                                                             (7 MEAN NOISE VOLTAGE)                                                                         N+ ENHANCED NPN TRANSISTOR 7A                        __________________________________________________________________________     10 hertz                                                                             3.20 nanovolts   2.97 nanovolts                                       100 hertz                                                                             4.73 nanovolts   4.18 nanovolts                                        1 kHz  3.18 nanovolts   2.91 nanovolts                                       __________________________________________________________________________

Although the reduction in measured noise voltage as a result ofproviding the N+ rings in the collector and base regions is not aspronounced as in the JFETs, the ratio of inactive N+ gettering regionarea to total NPN transistor area in those experiments is not as largeas would be desirable. Further experiments need to be performed withlarger ratios of N+ gettering region area to N type epitaxial regionarea to determine what the optimum ratio should be.

It should be noted that the above-mentioned Quan-Tec noise analyzermeasures noise voltage. In bipolar transistors, the noise current isalso important. The noise current can be computed from the noise voltageby placing a resistor in series with the base electrode of a transistorand taking measurements again using the Quan-Tec noise analyzer. Thefollowing equations provide a brief review of how this can beaccomplished. The basic noise equation is: ##EQU1## where I_(C)=collector current

β=hfo

q=1.6×10⁻¹⁹

K=flicker coefficient (due to recombination and generation of popcornnoise)

V_(T) =thermal voltage 0.0259

f=frequency

r_(b) =base resistance

e_(n) =measured noise voltage

At high frequencies, ##EQU2##

Therefore: ##EQU3##

This equation can now be solved for r_(b) : ##EQU4##

Once r_(b) is known, then measurements made with a resistance R_(s) inseries with the base can be used to calculate K at low frequencies.

The following equation applies when R_(s) is connected in series withthe base electrode: ##EQU5## where e_(ns) =noise measured with R_(s) inseries with the base.

Rather than solve these equations by hand, a simple program was writtento perform the calculations. The results of these measurements andcalculations are presented below.

    ______________________________________                                                             N+ Enhanced                                                                   NPN Transistor                                                                With Minimum Width                                                 Standard   N+ Rings in Base                                                   NPN Transistor                                                                           Region and Collector                                               7 of FIG. 3A                                                                             Region                                                   ______________________________________                                        Avg. e.sub.n (100 KhZ)                                                                     2.89 nanovolts                                                                             2.51 nanovolts                                      Avg. e.sub.ns (10 Hz)                                                                     19.79 nanovolts                                                                            15.57 nanovolts                                      β      680          650                                                  I.sub.C     200 microamperes                                                                           200 microamperes                                     r.sub.b     437.4 ohms   313.3 ohms                                           K           5.26 × 10.sup.-17                                                                    1.82 × 10.sup.-17                              ______________________________________                                    

It can be seen that for the N+ enhanced devices, the flicker coefficientof noise has been substantially reduced.

Finally, the noise current can be calculated using the equation:##EQU6##

The results are:

    ______________________________________                                                                 NPN Transistor                                                                With Minimum Width                                               Standard     N+ Rings in Base                                                 NPN Transistor                                                                             Region and Collector                                 Noise Current                                                                             7 of FIG. 3A Region                                               ______________________________________                                        i.sub.n     1.27 picoamps                                                                              .81 picoamps                                         ______________________________________                                    

Again, the noise current has been reduced by about 36 percent.

The above equations appear in various text books that discuss noise insemiconductor devices. For example, see the text "Analysis and Design ofIntegrated Circuits" by Gray and Meyer, 1977, published by John Wiley &Sons, Inc.

Those skilled in the art will appreciate that a decrease in the totalmeasured noise voltage at low frequency, i.e., 10 hertz or 100 hertz,actually corresponds to a much larger percentage decrease in the lowfrequency noise voltage, since the low frequency component of the totalnoise voltage is much less than the total noise voltage itself, andsince the remaining high frequency components of the total measurednoise voltage are not significantly influenced byrecombination-generation mechanisms and therefore are not affected byprovision of the large N+ gettering regions adjacent to the activeregions of the JFETs or bipolar transistors.

It should be noted that various temperature ramping cycles can beprovided to optimize the gettering by the N+ gettering regions 33 in theNPN transistors and JFETs described above. Once gettering has occurred,the trapped metallic impurities will remain trapped unless thetemperature of the wafer is raised to a sufficiently high level. For thedevices described above, I believe that gettering has occurred mainlyduring a gradual, 70 minute linear decline in the temperature from 900°Centigrade to 650° Centigrade in the presence of nitrogen, after a 900°Centigrade annealing step performed after implanting the top gate regionwith arsenic ions.

It should be noted that the reduction in noise voltage of the JFETs andbipolar transistors as a function of increasing ratios of inactive N+gettering region area to epitaxial N type region surface area diminishesas the ratio increases. For particular applications, the circuitdesigner will have to make a tradeoff between the amount of increase inoverall size of the integrated circuit and the amount of reduction innoise voltage achieved thereby.

It is believed to be a surprising result that substantial improvementsin total measured noise voltage of a JFET, bipolar transistor, or lownoise circuit utilizing such JFETs or transistors in the high gainsignal path can be achieved without substantially increasing the overallsize of the integrated chip.

While the invention has been described with respect to a number ofembodiments, those skilled in the art will be able to make variousmodifications to the described embodiment without departing from thetrue spirit and scope of the invention. It is intended that allstructures and techniques which are equivalent to those described hereinin that they perform substantially the same function in substantiallythe same way to achieve the same result are within the scope of theinvention.

I claim:
 1. A method of reducing noise in a semiconductor device,comprising the steps of:(a) providing a first region in a top surface ofa semiconductor wafer and providing a plurality of regions within thefirst region, some of the regions defining an electrically active regionin which current flows to cause the semiconductor device to operate; and(b) forming a gettering region of heavily doped, electrically inactivematerial in the top surface and located outside of and adjacent to theelectrically active region of the semiconductor device by producing ahigh concentration of surface damage in the semiconductor crystallattice in the top surface,the gettering region occupying at least about25 percent of the top surface area of the first region.
 2. The method ofclaim 1 including forming the gettering region in a configuration thatsubstantially surrounds the electrically active region of thesemiconductor device.
 3. The method of claim 1 including forming thehigh concentration of surface damage by forming an N+ region thatcomprises a first N+ gettering region.
 4. The method of claim 3including producing the first N+ gettering region simultaneously withthe step of forming N+ emitter regions elsewhere in a semiconductorwafer in which the semiconductor device is being formed.
 5. The methodof claim 4 including producing the gettering region to occupy apercentage of the top surface area of the first region in the range from25 to 75 percent.
 6. The method of claim 5 wherein the step (a) includesforming an electrically isolated N type epitaxial region comprising thefirst region and forming a P type base region in the N type epitaxialregion, and wherein the method includes forming an N+ emitter region inthe P type base region and simultaneously forming the N+ region thatcomprises the first N+ gettering region in the N type epitaxial regionin spaced relationship to the P type base region, to thereby form a lownoise bipolar transistor.
 7. The method of claim 6 including forming anN+ region that comprises a second N+ gettering region in the P type baseregion in spaced relationship to the N+ emitter region simultaneouslywith the forming of the N+ emitter region, and electrically shorting thesecond N+ gettering region to the P type base region.
 8. The method ofclaim 5 wherein step (a) includes forming an electrically isolated Ntype epitaxial region comprising the first region and forming a P typesoure region and a P type drain region in the N type epitaxial region,and wherein the method includes forming an N+ gate contact region in theN type epitaxial region in spaced relationship to the source region andthe drain region and simultaneously forming the N+ region that comprisesthe first N+ gettering region in the N type epitaxial region in spacedrelationship to the source and drain regions, to form a low noise fieldeffect transistor.
 9. The method of claim 5 including heating thesemiconductor wafer to a first temperature that is low enough to preventappreciable diffusion of doping impurities in the first region and theplurality of regions and is high enough to allow rapid diffusion of fastdiffusing metallic impurities to effectuate sufficiently rapid diffusionof metallic impurities in the vicinity of the electrically active regionto the first N+ gettering region and gradually ramping the temperaturedown to a second temperature at which diffusion of the metallicimpurities is insignificant, so as to substantially deplete the metallicimpurities from the vicinity of the electrically active region, tothereby avoid minority carrier recombination-generation at metallicimpurities in the electrically active region.
 10. The method of claim 9wherein the first temperature is about 900° Centigrade, the secondtemperature is about 650° Centigrade, and the duration of the ramping isabout one hour.
 11. A low noise semiconductor device including:(a) asemiconductor wafer having a top surface and an electrically isolatedfirst region therein; (b) a plurality of regions disposed within thefirst region at the top surface, the plurality of regions defining anelectrically active region in which a current flows to cause thesemiconductor device to operate, fast diffusing metallic impurities inthe semiconductor wafer in the vicinity of the electrically activeregion causing minority carrier recombination and generation to producelow frequency noise in the current; (c) a gettering region of heavilydoped, electrically inactive material comprised of a high concentrationof surface damage in the semiconductor crystal lattice and disposed inthe first region at the top surface in closely spaced relationship tothe electrically active region, the gettering region occupying about 25to 75 percent of the top surface area of the first region and trapping asufficient number of metallic impurities originally in the vicinity ofthe electrically active region such that low frequency noise in thecurrent is substantially reduced when the semiconductor device isoperated.
 12. The low noise semiconductor device of claim 11 wherein thefirst region is an N type epitaxial region having therein a P typesource region and a P type drain region, the electrically active regionincluding a lightly doped P type channel region, and an N+ gate contactregion located in spaced relationship to the source and drain regionsand the channel region, the N+ gate contact region having the samedoping type and same doping profile as the gettering region,whereby thelow noise semiconductor device is comprised of a junction field effecttransistor.
 13. The low noise semiconductor device of claim 11 whereinthe gettering region substantially surrounds the plurality of regions inthe first region.
 14. The low noise semiconductor device of claim 11wherein the first region is an N type epitaxial region having therein aP type base region and an N+ type emitter region disposed in the baseregion, the electrically active region including the emitter basejunction formed thereby, the N+ emitter region having the same dopingtype and same doping profiles as the gettering region,whereby the lownoise semiconductor device is comprised of an NPN transistor.
 15. Thelow noise semiconductor of claim 12 or 14 wherein the gettering regionincludes phosphorous atoms having a surface concentration of about 10²¹atoms per cubic centimeter.
 16. A low noise amplifying circuit formed ina semiconductor wafer and having a top surface and having an inputterminal receiving an output signal and an output terminal,comprising:(a) amplifying circuit means coupled between the inputconductor and the output conductor for amplifying the input signal toproduce an amplified output signal on the output conductor; and (b) aplurality of active semiconductor devices interconnected in theamplifying circuit means to form an AC signal path between the inputconductor and the output conductor, some of active devices substantiallyamplifying the input signal, wherein each of the active devices thatsubstantially amplifies the input signal includes an electricallyisolated first region in the semiconductor wafer, a plurality of regionsdisposed within the first region at the top surface, the plurality ofregions defining an electrically active region in which a current flowsto cause the semiconductor device to operate, fast diffusing metallicimpurities in the semiconductor wafer in the vicinity of theelectrically active region causing minority carrier recombination andgeneration to produce low frequency noise in the current, a getteringregion of heavily doped, electrically inactive material comprised of ahigh concentration of surface damage in the semiconductor crystallattice and disposed in the first region at the top surface in closelyspaced relationship to the electrically active region, the getteringregion occupying about 25 to 75 percent of the top surface area of thefirst region and trapping a sufficient number of metallic impuritiesoriginally in the vicinity of the electrically active region such thatlow frequency noise in the current is substantially reduced when theamplifying circuit is operated.